1. Field of the Invention
This invention relates to a process and structure for neutralizing crystalline defects in a charged coupled device structure, in particular, for isolating the defect from the remaining substrate with a PN junction.
2. Description of the Prior Art
The operation of a charged coupled device, commonly referred to as CCD, basically consists of storing electric charge at the surface of a semiconductor in which a potential well has been created, and moving this charge across the surface of the semiconductor by applying sequentially increasing electric potentials across the semiconductor surface.
By employing a series of metal gates insulated from a silicon substrate by a layer of silicon dioxide, a depletion region is formed under each of the metal gates by applying the appropriate voltage to the appropriate gate electrode. The potential well created by the depletion region under the gate electrode attracts a charge flow into the potential well, and acts as a storage well for the charge packet. By applying a series of sequentially increasing electric pulses to the gate electrodes, the charge packet may be transported into each successive neighboring potential well. The charge packet is thereby progressively transported along an array of gate regions by the sequential application of the appropriate electric pulses.
Although the immediate application of a charge coupled device is to digital electronics, its application may be expanded to analog delay lines whereby the various amounts of charge stored in the potential well are given numeric significance. When the amount of charge stored in the potential well is given numeric significance, crystalline defects in the semiconductor substrate have serious adverse effects on device operation. Defects in the semiconductor substrate, which tend to aggregate near the surface of the semiconductor, interact with the potential well so as to introduce additional charge flow into the potential well. This defect is a region of the semiconductor where the single crystal structure is not maintained and generation-recombination rates are greater than elsewhere in the material. When the defect intersects the potential well, the increased generation-recombination rate causes a flow of carriers into the potential well. This additional charge flow into the potential well increases the amount of charge stored in the charge packet, thereby undesirably altering the analog characteristics of the charge packet. The details of the mechanism by which such additional charge flows into the potential well has received extensive treatment in technical literature. For purposes of simplicity, such mechanisms will not be discussed here.
Neutralizing the effect of the crystalline defect and thereby preventing additional charge flow into the potential well would improve the operating characteristics of the charge coupled device and improve its reliability as an analog delay line.